The present invention relates generally to data communications between electronic devices and particularly, but not by way of limitation, to a driver for high speed data communications.
Of the many trends apparent in the electronic industry, two noteworthy examples include increased processor speeds and reduced power consumption. The trend toward increased processor speed enables execution of sophisticated and complex calculations at ever increasing speeds. Commensurate with an increased speed is the reduced time available in which digital data may be transmitted and received. The trend toward reduced power consumption facilitates devices operable with battery power or other means having a reduced power supply capacity. Also, low power devices dissipate less heat which further enables a higher component density and yet provide reliable operation.
The limited amount of available space on an integrated circuit often constrains the placement of components, including such circuits as drivers. A driver circuit is used to receive an input signal and provides an output signal on interconnect lines. In many applications, a driver requires connections to multiple power supplies. For example, power supply traces often are not available or are unduly problematic.
For efficiency reasons, the output impedance of a driver should be matched to the load of the interconnect lines. Manufacturing tolerances associated with the production of driver circuits may yield some drivers more closely matched than other drivers. In addition, variations in voltage levels can be problematic in the pursuit of high speed reliable data communications. For example, high voltages may result in very fast slew rates and thus lead to excessive current drain during such rapid swings. Ringing of the output voltage levels following level transitions may further delay the sensing of a level. Temperature changes can also have deleterious effects. For example, excessive operating temperature, such as may result from a suboptimal cooling fan, can degrade driver circuit performance and further limit reliable clock speeds, or lead to processing errors.
What is needed in the art is a driver having low power requirements which is reliably operable at a high data communication rate with compensation for variations in process, voltage and temperature.
The above mentioned problems associated with driver systems, and other problems, are addressed by the present invention and will be understood by reading and studying the following specification.
In particular, an illustrative embodiment of the present invention includes an integrated circuit driver having an output node for coupling to a load and providing a first and second voltage level at a predetermined impedance. The first and second voltage level correspond to a logic high and logic low level, respectively. The output node also provides a high impedance state. The driver includes a first switched resistive element coupled to the output node and also coupled to a first voltage source, a second switched resistive element coupled to the output node and also coupled to a second voltage source and a third switched resistive element coupled to the output node and also coupled to the second voltage source. The first switched resistive element is actuated by a first control line coupled to the first switched resistive element. The second switched resistive element is actuated by a second control line coupled to the second switched resistive element. The third switched resistive element is actuated by a third control line coupled to the third switched resistive element. The load is a resistive load coupled to a third voltage source. The first voltage level, the second voltage level and the predetermined impedance remain substantially constant with variations in manufacturing process, variations in the first voltage source, variations in the second voltage source and variations in operating temperature.
In one embodiment, the first switched resistive element includes a PFET. In one embodiment, the second switched resistive element comprises an NFET. In one embodiment, the third switched resistive element comprises an NFET. In one embodiment, the ratio of the resistance of the second switched resistive element to the resistance of the third switched resistive element is approximately five to one. In one embodiment, the first voltage source is approximately 1.8 volts.
One illustrative embodiment of the present invention includes a method including receiving a data signal, adjusting a first resistance coupled to a first supply voltage, based on a manufacturing process, the first supply voltage and a temperature, adjusting a second resistance coupled to a second supply voltage, based on the manufacturing process, the first supply voltage and the temperature and adjusting a third resistance coupled to the second supply voltage, based on the manufacturing process, the first supply voltage and the temperature.
One illustrative embodiment of the present invention includes a method including selecting a resistance of a divider network based on a manufacturing process, a supply voltage and a temperature, selecting an edge rate of a driver coupled to the divider network, the selected edge rate based on the manufacturing process, the supply voltage and the temperature, receiving a data signal and providing an output based on the data signal, the resistance, and the edge rate. In one embodiment, selecting an edge rate of a driver coupled to the divider network includes maintaining a substantially constant edge rate. In one embodiment, providing an output includes turning on a PFET transistor and turning off an NFET transistor. In one embodiment, selecting a resistance of a divider network includes selecting a plurality of parallel resistance elements. In one embodiment, selecting a resistance of a divider network comprises executing programming for selecting resistance elements from a plurality of switchable resistance elements. In one embodiment, selecting an edge rate of a driver coupled to the divider network comprises selecting a plurality of parallel resistance elements. In one embodiment, selecting an edge rate of a driver coupled to the divider network comprises executing programming for selecting resistance elements from a plurality of switchable resistance elements. One embodiment includes receiving a tristate enable signal and actuating a switchable resistance element in response to the tristate enable signal. In one embodiment, actuating a switchable resistance element comprises actuating a programmable inverter.
One illustrative embodiment of the present invention includes a driver having an output section, a first predriver section and a second predriver section. The output section includes an output node, a plurality of P-nodes, a first plurality of P-channel transistors, a plurality of N-nodes, a first plurality of N-channel transistors and a second plurality of N-channel transistors. Each P-channel transistor of the first plurality of P-channel transistors has a source coupled to a supply voltage and a drain coupled to the output node, wherein each of the plurality of P-nodes is coupled to a gate of each P-channel transistor of the first plurality of P-channel transistors. Each N-channel transistor of the first plurality of N-channel transistors has a drain coupled to the output node and a source coupled to a ground potential relative to the supply voltage wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the first plurality of N-channel transistors. Each N-channel transistor of the second plurality of N-channel transistors has a drain coupled to the output node and a source coupled to the ground potential wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the second plurality of N-channel transistors. The first predriver section includes a P-output node, a second plurality of P-channel transistors, a third plurality of N-channel transistors, an N-output node, a third plurality of P-channel transistors and a fourth plurality of N-channel transistors. Each P-channel transistor of the second plurality of P-channel transistors has a source coupled to the supply voltage and a drain coupled to the P-output node, wherein each of the plurality of P-nodes is coupled to a gate of each P-channel transistor of the second plurality of P-channel transistors. Each N-channel transistor of the third plurality of N-channel transistors has a drain coupled to the P-output node and a source coupled to the ground potential and wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the third plurality of N-channel transistors. Each P-channel transistor of the third plurality of P-channel transistors has a source coupled to the supply voltage and a drain coupled to the N-output node, wherein each of the plurality of P-nodes is coupled to a gate of each P-channel transistor of the third plurality of P-channel transistors. Each N-channel transistor of the fourth plurality of N-channel transistors has a drain coupled to the N-output node and a source coupled to the ground potential and wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the fourth plurality of N-channel transistors. The P-output node is coupled to the source of each P-channel transistor of the first plurality of P-channel transistors and the N-output node is coupled to the source of each N-channel transistor of the first plurality of N-channel transistors. The second predriver section includes a T-node, a fourth plurality of P-channel transistors, and a fifth plurality of N-channel transistors. Each P-channel transistor of the fourth plurality of P-channel transistors has a source coupled to the supply voltage and a drain coupled to the T-node, wherein each of the plurality of P-nodes is coupled to a gate of each P-channel transistor of the fourth plurality of P-channel transistors. Each N-channel transistor of the fifth plurality of N-channel transistors has a drain coupled to the T-node and a source coupled to the ground potential and wherein each of the plurality of N-nodes is coupled to a gate of each N-channel transistor of the fifth plurality of N-channel transistors. The T-node is coupled to the source of each of the second plurality of N-channel transistors of the output section.
In one embodiment, the P-channel transistors are PFET transistors and the N-channel transistors are NFET transistors. In one embodiment, the first plurality of P-channel transistors includes one P-channel transistor having an effective resistance lower than an effective resistance of each of the other P-channel transistors in the first plurality of P-channel transistors. In one embodiment, the first plurality of N-channel transistors includes one N-channel transistor having an effective resistance lower than an effective resistance of each of the other N-channel transistors in the first plurality of N-channel transistors. In one embodiment, the second plurality of N-channel transistors includes one N-channel transistor having an effective resistance lower than an effective resistance of each of the other N-channel transistors in the second plurality of N-channel transistors. In one embodiment, the ratio of the effective resistance of the second plurality of N-channel transistors to the effective resistance of the first plurality of N-channel transistors is approximately five to one.